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NXE3400B

Semiconductor foundries are pushing ahead with extreme ultraviolet lithography (EUV) integration, just there are still formidable barriers to deploying the applied science at 5nm and below.

There are several bug that EUV must solve (or proceed solving) in order to serve as a replacement for existing 193nm lithography solutions. ASML is still working to develop a pellicle — the membrane that serves as a dust encompass over the photomask — that doesn't blot as well much light. Tools like the NXE 3400B that nosotros saw when we toured GlobalFoundries a few weeks dorsum accept support and installation requirements that dwarf conventional lithographic tools, and a corresponding need to evangelize dramatically better toll structures to justify their own utilize.

According to a recent writeup in IEEE Spectrum, the non-profit R&D middle Imec, which is a leading enquiry center in EUV lithography, has seen meaning issues when using EUV to compose features at 5nm. The rate of stochastic effects is significantly college than is adequate for modern manufacturing.

A stochastic effect is an effect that appears randomly, without existence linked to a specific dose level, merely whose probability is proportional to the forcefulness of the dose. In semiconductors, these effects produce defects that can sabotage or damage a given microprocessor. What Imec has establish suggests that these effects are common enough at 5nm to be a major barrier, requiring new approaches to metrology and boosted technological solutions. Sometimes, the spaces between the narrow etched trenches were too narrow, leading to so-called 'microconnections' between features that aren't meant to be connected. Other times, necessary features fail to print.

GFEUV

GlobalFoundries roadmap for EUV integration. Photo past EETimes

GlobalFoundries showed a diagram suggesting that EUV may be integrated gradually, starting with MOL (middle-of-line), before beingness integrated into other manufacturing areas. In this model, EUV doesn't see full integration until 2024 -2026. Equally EETimes also discusses, at that place are nevertheless barriers to full deployment at about every step in the procedure, from metrology to resists.

The Problem of Perfection

If y'all want a 10,000-foot overview of the problem, think of it in these terms: Imagine you lot've been asked to draw a straight line with a pencil and a slice of paper. Nigh people tin can draw a reasonably straight line costless-manus. At present, imagine yous've been asked to depict an increasingly straight line. Offset, yous reach for a ruler. When that's no longer sufficient, you might utilise other mechanical guides.

Eventually, however, that's no longer enough. You might movement to a robotic arm with a perfectly maintained grip and calibrated movement and motility sensors that ensure the line is laid down perfectly. By that, y'all might have to find a new type of writing musical instrument capable of laying downwardly a mark with fifty-fifty less moment-to-moment variation in graphite deposition. You might invest in a specific kind of paper that's been engineered for less surface variance and superior "flatness." Every bit the acceptable variance in a directly line moves from "eyeball it" to "nanometers," the tools you need to generate that line go increasingly complex.

That, in a very large nutshell, is what's happening in modern lithography. EUV exists because modern feature sizes are so small, they can't be imaged with existing 193nm lithography without relying on multiple photomasks, which dramatically increases the cost of the device. But EUV is such a fundamentally different approach to what'southward been deployed before, it creates an entirely new fix of potential problems and interactions with other materials in the manufacturing process, as well every bit all of the other problems associated with shrinking process nodes and finding more ways to pack transistors more tightly together. Equally feature sizes compress, defects that used to have no affect at present threaten a pattern. This has meaning implications for fleck yields, which in turn has significant implications for chip toll.

Lithography costs

EUV is expected to bring lithography costs under control, eventually. This slide is from 2022 but shows the trends clearly. Care for it as an estimate example of cost improvement.

Images like the above, which testify EUV lithography dramatically reducing costs, are prefaced on the idea that foundries tin hit equal yield targets with and without EUV. If EUV yields run lower than conventional lithography yields, that's going to piece of work directly confronting any button to move EUV into the mainstream.

EUV is an Economic Play

I desire to striking this directly, considering I've seen this question come upwards in multiple stories. In many cases, when semiconductor companies denote a manufacturing breakthrough, it's in the proper name of making products faster. EUV doesn't really have any implications for transistor speed, at least non direct.

The reason everyone is charging ahead with EUV is because the economic science of semiconductor manufacturing are on a standoff course with the key limits of 193nm lithography. Modernistic chips rely on multiple photomasks to compose their features, in a procedure referred to every bit multi-patterning. Today, quadruple design is commonly used for 14/16nm devices. But the but way to continue moving downwards would exist to proceed introducing more than mask steps. Each mask costs money and each exposure takes time. Fries that used to accept 30-40 mask steps might have 70-90 today and well over a hundred in the future. The reason foundries continue to earn substantial amounts of revenue on older process nodes is because many customers meet no do good (and sharply increased costs) from moving to newer nodes. Multi-patterning is a large part of why.

Deploying EUV doesn't merely clear the way for future node shrinks. It slashes costs on the nodes where it's deployed, hopefully giving customers who otherwise wouldn't carp upgrading to a new node reasons to do and then. That's why GF, Intel, Samsung, and TSMC are all plunging ahead to deploy the applied science even as Imec sounds the alarm on the difficulties ahead. It'due south not an either/or situation. EUV has major problems notwithstanding to be solved and EUV is a necessity for moving the industry forward.

The next few years are going to be existent interesting.